The present invention relates to integrated circuit (IC) interconnects, and more specifically, to collar formation for chamfer-less and chamfered vias.
An integrated circuit (i.e. chip) can have multiple metal layers, also referred to as metal lines. While components (e.g., logic gates, latches) within the same metal layer can be connected by wiring, components on two different metal layers are interconnected by a vertical electrical connection called a via. Thus, multiple metal layers Mx (e.g., M1, M2, . . . , Mn) can have multiple via layers Vx (e.g., V1, V2, . . . , Vn-1) to interconnect components. A via can be chamfered (i.e., wider at Mx+1 level than at Mx level, or via with slanted side walls) or chamfer-less (i.e., a column between the Mx+1 and Mx levels, or via with vertical sidewalls).